Articles with public access mandates - Igor Loi - European CommissionLearn more
Not available based on mandate: 1
Logic-base interconnect design for near memory computing in the smart memory cube
E Azarkhish, C Pfister, D Rossi, I Loi, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 210-223, 2016
Available based on mandate: 12
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters
J Chen, I Loi, E Flamand, G Tagliavini, L Benini, D Rossi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (4), 456-469, 2023
Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode
D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ...
IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021
4.4 A 1.3 TOPS/W@ 32GOPS fully integrated 10-core SoC for IoT end-nodes with 1.7 μW cognitive wake-up from MRAM-based state-retentive sleep mode
D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021
Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing
A Pullini, D Rossi, I Loi, G Tagliavini, L Benini
IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019
The quest for energy-efficient i $ design in ultra-low-power clustered many-cores
I Loi, A Capotondi, D Rossi, A Marongiu, L Benini
IEEE Transactions on Multi-Scale Computing Systems 4 (2), 99-112, 2017
Neurostream: Scalable and energy efficient deep learning with smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017
A hybrid instruction prefetching mechanism for ultra low-power multicore clusters
M Payami, E Azarkhish, I Loi, L Benini
IEEE Embedded Systems Letters 9 (4), 125-128, 2017
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
A heterogeneous multicore system on chip for energy efficient brain inspired computing
A Pullini, F Conti, D Rossi, I Loi, M Gautschi, L Benini
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (8), 1094-1098, 2017
High performance AXI-4.0 based interconnect for extensible smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
A modular shared L2 memory design for 3-D integration
E Azarkhish, D Rossi, I Loi, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (8 …, 2014
A multi banked—multi ported—non blocking shared L2 cache for MPSoC platforms
I Loi, L Benini
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
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