Articles with public access mandates - Igor Loi - Swiss National Science FoundationLearn more
Not available based on mandate: 6
Energy-efficient near-threshold parallel computing: The PULPv2 cluster
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ...
Ieee Micro 37 (5), 20-31, 2017
A self-aware architecture for PVT compensation and power nap in near threshold processors
D Rossi, I Loi, A Pullini, C Müller, A Burg, F Conti, L Benini, P Flatresse
IEEE Design & Test 34 (6), 46-53, 2017
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC
P Meloni, G Deriu, F Conti, I Loi, L Raffo, L Benini
2016 International Conference on ReConFigurable Computing and FPGAs …, 2016
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA
P Meloni, G Deriu, F Conti, I Loi, L Raffo, L Benini
Proceedings of the ACM International Conference on Computing Frontiers, 376-383, 2016
193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ...
Solid-State Electronics 117, 170-184, 2016
Available based on mandate: 11
Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing
A Pullini, D Rossi, I Loi, G Tagliavini, L Benini
IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019
Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing
A Pullini, D Rossi, I Loi, A Di Mauro, L Benini
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
Neurostream: Scalable and energy efficient deep learning with smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE transactions on very large scale integration (VLSI) systems 25 (10 …, 2017
A heterogeneous multicore system on chip for energy efficient brain inspired computing
A Pullini, F Conti, D Rossi, I Loi, M Gautschi, L Benini
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (8), 1094-1098, 2017
PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision
F Conti, D Rossi, A Pullini, I Loi, L Benini
Journal of Signal Processing Systems 84, 339-354, 2016
A− 1.8 V to 0.9 V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
D Rossi, A Pullini, M Gautschi, I Loi, FK Gurkaynak, P Flatresse, L Benini
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015
High performance AXI-4.0 based interconnect for extensible smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
A Logic-base interconnect for supporting near memory computation in the hybrid memory cube
E Azarkhish, D Rossi, I Loi, L Benini
Proceedings of the 2nd Workshop on Near-Data Processing, 2014
Energy-efficient vision on the PULP platform for ultra-low power parallel computing
F Conti, D Rossi, A Pullini, I Loi, L Benini
2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014
A modular shared L2 memory design for 3-D integration
E Azarkhish, D Rossi, I Loi, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (8 …, 2014
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