Authors
Sreehari Veeramachaneni, M Kirthi Krishna, Lingamneni Avinash, Sreekanth Reddy, MB Srinivas
Publication date
2007/3/9
Conference
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07)
Pages
343-350
Publisher
IEEE
Description
In view of increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture for efficient 1-digit decimal addition of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders and floating decimal-point arithmetic, is proposed. Based on this 1-digit BCD adder, novel architectures for higher order (n-digit) BCD adders such as ripple carry adder and carry look-ahead adder are derived. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed 1-digit BCD adder achieves an improvement of 40% in delay. The 16-digit BCD look-ahead adder using prefix logic is shown to perform at least 80 …
Total citations
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Scholar articles
S Veeramachaneni, MK Krishna, L Avinash, S Reddy… - IEEE Computer Society Annual Symposium on VLSI …, 2007