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The comparator is of paramount importance in many digital systems as it plays an important role in almost all hardware sorters. In this paper, the design of a 32-bit comparator is proposed based on the logic of a parallel prefix adder. This circuit computes only the final carry or borrow using the structure of a modified prefix adder and employs it to compare the two given numbers, thereby achieving a latency of O(log n). The proposed comparator circuit has been compared (both qualitatively and quantitatively) with the existing ones and is shown to achieve an efficiency of 21% in overall delay and reduction of 30% in power.