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Bit-counting implementations are used to count the number of 1 s in a given computer word. There are several techniques to implement bit-counting operation. These techniques are either software algorithms or specialized hardware techniques. The hardware implementations require dedicate hardware supported in the processor or associated math co-processor. The performance of th hardware-supported bit-counting was found to be superior to most software implementations (such a serial shifting). In this paper, a new hardware implementation of bit-counting routine is presented tha reduces the number of logic gates and the delay in comparison with existing implementations. Th performance of the proposed hardware bit-counting implementations is further investigated an evaluated.