Inventors
Peter West, Ronald Harlan, Steven L Kosier
Publication date
2004/10/12
Patent office
US
Patent number
6804809
Application number
10283834
Description
(57) ABSTRACT A method to create a layout of a Semiconductor device for the purpose of fabricating the Semiconductor device involves first providing a plurality of partial-area layout cells and then generating the layout of the Semiconductor device by placing the plurality of the partial-area layout cells together. The layout can be conveniently expanded to a desirable size by replicating or repeating certain repeatable cells.
Total citations
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