Authors
Yao-Jen Lee, Yu-Lun Lu, Fu-Kuo Hsueh, Kuo-Chin Huang, Chia-Chen Wan, Tz-Yen Cheng, Ming-Hung Han, Jeff M Kowalski, Jeff E Kowalski, Dawei Heh, Hsi-Ta Chuang, Yiming Li, Tien-Sheng Chao, Ching-Yi Wu, Fu-Liang Yang
Publication date
2009/12/7
Conference
2009 IEEE International Electron Devices Meeting (IEDM)
Pages
1-4
Publisher
IEEE
Description
For the first time, CMOS TFTs of 65 nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF 2 for p-MOS TFTs and P 31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
Total citations
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Scholar articles
YJ Lee, YL Lu, FK Hsueh, KC Huang, CC Wan… - 2009 IEEE International Electron Devices Meeting …, 2009