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In this work, we are proposing the ZUCL framework for implementing and running OpenCL applications for the latest Xilinx ZYNQ UltraScale+ platform. ZUCL is a holistic framework addressing the FPGA OS infrastructure, high level synthesis (HLS) module implementation as well as the runtime management. ZUCL enables partial reconfiguration (PR) on this platform by providing an infrastructure featuring multiple adjacent PR regions having an identical resource layout. This allows users building their hardware modules once but instantiating them multiple times in the provided regions in a hot plug-and-play manner as well as implementing different sized modules that can share the reconfigurable resources. An automatic physical implementation backend based on templates allows implementing OpenCL kernels into hardware modules all the way from OpenCL descriptions to relocatable accelerator bitstreams in a …