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With passing over the 1M LUT barrier, FPGA technology is heading into new challenges and opportunities. While the present ASIC-like design methodology and tools will struggle to scale with such huge devices, providing partial run-time reconfiguration will be become obligatory for dealing with long configuration times and the increasing vulnerability to single event upsets. Within the COSRECOS project, we address these issues by developing methods and tools that allow to compose systems rapidly by plugging together fully physically implemented components. Moreover, by allowing a hot-swapping of such components, the tremendous advantages of partial run-time reconfiguration can be utilized. This talk will give an overview of recent trends, our present research activities, and will discuss open issues.