Authors
Tobias Blickle, Jürgen Teich, Lothar Thiele
Publication date
1998/1
Journal
Design Automation for Embedded Systems
Volume
3
Pages
23-58
Publisher
Kluwer Academic Publishers
Description
In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model …
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Scholar articles
T Blickle, J Teich, L Thiele - Design Automation for Embedded Systems, 1998