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Embedded systems often involve transmitting feedback signals between multiple control tasks that are implemented on different electronic control units communicating via a shared bus. For ensuring stability and control performance, such designs require all control signals to be delivered within a specified deadline, which is ensured through appropriate timing or schedulability analysis. In this brief, we study controller design that allows control feedback signals to occasionally miss their deadlines. In particular, we provide analytical bounds on deadline misses such that the control loop retains its stability and meets its control performance requirements. We argue that such relaxation allows us to 1) use lower quality communication resources (e.g., event-triggered instead of time-triggered communication) and 2) provide more flexibility-e.g., use simulation-in communication timing analysis since analytical worst-case …