Inventors
Alonso Morgado, Serena Porrazzo, Francesco Cannillo
Publication date
2015/2/24
Patent office
US
Patent number
8963754
Application number
14022351
Description
A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.
Total citations
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Scholar articles
A Morgado, S Porrazzo, F Cannillo - US Patent 8,963,754, 2015