Authors
Alvin R Lebeck, David R Raymond, Chia-Lin Yang, Mithuna S Thottethodi
Publication date
1999
Conference
Euro-Par’99 Parallel Processing: 5th International Euro-Par Conference Toulouse, France, August 31–September 3, 1999 Proceedings 5
Pages
1251-1254
Publisher
Springer Berlin Heidelberg
Description
As the importance of cache performance increases, allowing software to assist in cache management decisions becomes an attractive alternative. This paper focuses primarily on a mechanism for software to convey information to the memory hierarchy. We introduce a single instruction—called TAG—that can annotate subsequent memory references with a number of bits, thus avoiding major modifications to the instruction set. Simulation results show that annotating all memory reference instructions in the SPEC95 benchmarks increases execution time between 0% and 2% for both statically and dynamically scheduleded processors. We show that exposing cache management mechanisms to software can decrease the execution time of three media benchmarks (epic, pegwit, ijpeg) between 11% and 17% speedups on a 4-issue dynamically scheduled processor.
Total citations
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Scholar articles
AR Lebeck, DR Raymond, CL Yang, MS Thottethodi - Euro-Par'99 Parallel Processing: 5th International Euro …, 1999