Authors
Igor Loi, Luca Benini
Publication date
2010/3/8
Conference
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
Pages
99-104
Publisher
IEEE
Description
Historically, processor performance has increased at a much faster rate than that of main memory and up-coming NoC-based many-core architectures are further tightening the memory bottleneck. 3D integration based on TSV technology may provide a solution, as it enables stacking of multiple memory layers, with orders-of-magnitude increase in memory interface bandwidth, speed and energy efficiency. To fully exploit this potential, the architectural interface to vertically stacked memory must be streamlined. In this paper we present an efficient and flexible distributed memory interface for 3D-stacked DRAM. Our interface ensures ultra-low-latency access to the memory modules on top of each processing element (vertically local memory neighborhoods). Communication to these local modules do not travel through the NoC and takes full advantage of the lower latency of vertical interconnect, thus speeding up …
Total citations
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Scholar articles
I Loi, L Benini - 2010 Design, Automation & Test in Europe Conference …, 2010