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Charge induced pattern distortions in low voltage electron beam lithography in the energy range of 1 to 5 kV were investigated. Pattern distortion on conducting substrates such as silicon was found to be small, while significant pattern placement errors and pattern distortions were observed in the case of electrically insulating substrates caused by charge trapping and deflection of the incident electron beam. The nature and magnitude of pattern distortions were found to be influenced by the incident electron energy, pattern size, electrical conductivity, and secondary electron emission coefficient of the substrate. Theoretical modeling predicts the electron beam deflection to be directly proportional to the trapped surface charge density and inversely proportional to the accelerating voltage.