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This paper presents an efficient ternary serial adder for nanotechnology employing negative, positive and standard ternary logics. Multiple-valued logic results in chips with more density, less complexity and high-bandwidth data transfer. The unique properties of CNTFETs such as the capability of adapting the desired threshold voltage by changing the diameters of the nanotubes and same carrier mobility for the n-type and p-type devices play an important role in designing this circuit. The proposed design method considerably reduces the number of required devices of a ternary serial adder. In addition, the results of the simulations conducted using HSPICE with the Stanford comprehensive 32 nm CNTFET model, demonstrate improvements in terms of speed and power-delay product as compared to the cutting-edge CNTFET-based ternary designs.