View article

This paper presents a single-ended low-power 7T SRAM cell in FinFET technology. This cell enhances read performance by isolating the storage node from the read path. Moreover, disconnecting the feedback path of the cross-coupled inverters during the write operation enhances WSNM by nearly 7.7X in comparison with the conventional 8T SRAM cell. By using only one bit-line, this cell reduces power consumption and PDP compared to the conventional 8T SRAM cell by 82% and 35%, respectively.