Authors
Aziz Ahmedsaid, Abbes Amira, Ahmed Bouridane
Publication date
2003/12/17
Conference
Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT)(IEEE Cat. No. 03EX798)
Pages
35-42
Publisher
IEEE
Description
This paper presents an efficient systolic array for the computation of the Singular Value Decomposition (SVD). The proposed architecture is three times more efficient and faster than the Brent, Luk, Van Loan (BLV) SVD systolic array. The architecture has been implemented efficiently on FPGA using a high level language for hardware design "Handel-C".
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Scholar articles
A Ahmedsaid, A Amira, A Bouridane - Proceedings. 2003 IEEE International Conference on …, 2003