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An 80-ns 1-Mb multiport video random-access memory (VRAM) can be organized as 128 K*8 or 256 K*4. Uninterrupted serial data streams of 70 MHz are achieved by combining pipelining and interleaving techniques with an internally triggered automatic memory-to-register transfer mechanism. DRAM bandwidth is enhanced by a block WRITE feature which can write as many as four column address locations in every CAS cycle. The write-per-bit feature has been expanded by including an on-chip write-per-bit latch and an extended mode of operation to simplify its use in a wider range of systems. The VRAM is fabricated in a 1 mu m CMOS technology using double-level poly/polycide, single level metal, and trench DRAM storage capacitors for high noise immunity.< >