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This paper presents a novel parallel pipeline FFT processor especially tailored for Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) Ultra Wideband (UWB) system, which was defined by ECMA International. The proposed Radix 2 ² Parallel Pipeline processor, which employs two parallel data path Radix 2 ² algorithm and single-path delay feedback (SDF) pipeline architecture, is a small-area and low-power-consumption solution for MB-OFDM UWB system. Both FPGA Xilinx Virtex4 and ASIC 90 nm technology, 1 V supply voltage targeted synthesis results of this architecture are presented. It is shown from the results that, due to the revised algorithm and novel architecture, the required clock frequency is 264 MHz to meet the ECMA requirement. Meanwhile, the required gates are 39000 without testing block and the corresponding area is 181140 ¿m ² .