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In this paper the application of the boundary element method to the layout verification of VLSI designs is described. The methods for the calculation of interconnection capacitances and substrate resistances with the use of problem specific Green's functions are also described. The derivation of these functions for multilayer structures is presented. Emphasis is on computational efficiency and practical accuracy. These are achieved by the type of the Green's functions and an appropriate model reduction technique. The methods are implemented in the layout extractor Space.