Authors
Jaume Abella, Francisco J Cazorla, Eduardo Quiñones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat
Publication date
2011/7/13
Conference
On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International
Pages
240-245
Publisher
IEEE
Description
Performance demand of Critical Real-Time Embedded (CRTE) systems implementing safety-related system features grows at an exponential rate. Only modern semiconductor technologies can satisfy CRTE systems performance needs efficiently. However, those technologies lead to high failure rates, thus lowering survivability of chips to unacceptable levels for CRTE systems. This paper presents SESACS architecture (Surviving Errors in SAfety-Critical Systems), a paradigm shift in the design of CRTE systems. SESACS is a new system design methodology consisting of three main components: (i) a multicore hardware/firmware platform capable of detecting and diagnosing hardware faults of any type with minimal impact on the worst-case execution time (WCET), recovering quickly from errors, and properly reconfiguring the system so that the resulting system exhibits a predictable and analyzable degradation in …
Total citations
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Scholar articles
J Abella, FJ Cazorla, E Quinones, A Grasset, S Yehia… - 2011 IEEE 17th International On-Line Testing …, 2011