Authors
Andrew S Cassidy, John V Arthur, Filipp Akopyan, Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Michael V Debole, Steven K Esser, Carlos Ortega Otero, Jun Sawada, Brian Taba, Arnon Amir, Deepika Bablani, Peter J Carlson, Myron D Flickner, Rajamohan Gandhasri, Guillaume J Garreau, Megumi Ito, Jennifer L Klamo, Jeffrey A Kusnitz, Nathaniel J McClatchey, Jeffrey L McKinstry, Yutaka Nakamura, Tapan K Nayak, William P Risk, Kai Schleupen, Ben Shaw, Jay Sivagnaname, Daniel F Smith, Ignacio Terrizzano, Takanori Ueda, Dharmendra Modha
Publication date
2024/2/18
Conference
2024 IEEE International Solid-State Circuits Conference (ISSCC)
Volume
67
Pages
214-215
Publisher
IEEE
Description
The Deep Neural Network (DNN) era was ushered in by the triad of algorithms, big data, and more powerful hardware processors for training large-scale neural networks. Now, the ubiquitous deployment of DNNs for neural inference in edge, embedded, and data center applications demands more power-efficient hardware processors, while attaining increasingly higher computational performance. To address this Inference Challenge, we developed the NorthPole Architecture and implemented a NorthPole Chip instantiation [1, 2].
Total citations
20241
Scholar articles
AS Cassidy, JV Arthur, F Akopyan, A Andreopoulos… - 2024 IEEE International Solid-State Circuits …, 2024