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This work illustrates the most effective way of utilizing the ferroelectricity for tunneling field-effect transistors (TFETs). The ferroelectric (Hf 0.5 Zr 0.5 O 2) in shunt with gate-dielectric is utilized as an optimized metal–ferroelectric–semiconductor (OMFS) option to improve the internal voltage (V int) for ample utilization of polarization and electric fields of Hf 0.5 Zr 0.5 O 2 across the tunneling region. The modeling of V int signifies 0.15–1.2 nm reduction in tunneling length (λ) than the nominal metal–ferroelectric–insulator–semiconductor (MFIS) option. Furthermore, the TFET geometry with the scaled-epitaxy region as vertical TFET (VTFET), strained Si 0.6 Ge 0.4 as source, and gate-all-around nanowire options are used as an added advantage for further enhancement of TFET's performance. As a result, the proposed design (OMFS-VTFET) achieves superior DC and RF performances than the MFIS option of TFET. The …