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We estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes. Devices with various dielectric spacers from low- to high-κ including asymmetric dual spacers (ADS) are considered. More than 31% boost on the normalized on-state currents is observed for the explored devices with high-κ and ADS spacers. Similarly, for the normalized off-state currents, more than 50% reduction is achieved. The largest magnitude of the RTN (ΔI _D /I _D ×100%) is 6.7% for the nominal GAA Si NS MOSFET with an effective channel width of 40-nm.