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A delay circuit includes a? rst and a second switching transistor, each of which has a control electrode and a? rst and a second main electrode, a? rst and a second input of the delay circuit being coupled to the control electrode of the? rst switching transistor and the second switching transistor, respectively. A? rst and a second output of the delay circuit are coupled to the second electrode of the? rst and the second switching transistors, respectively. The? rst elec trodes of the? rst and the second switching transistors are coupled to one another and, via a current source, to a? rst power supply terminal. The outputs are coupled to a second power supply terminal via respective load circuits. Respec [56] References Cited tive clamp circuits are coupled to the outputs in order to limit maximum attainable diiferences between a voltage on the US. PATENT DOCUlVIENTS second power supply terminal on the one side and a …