Authors
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Gianluca Lamanna, Alessandro Lonardo, F Lo Cicero, Pier Stanislao Paolucci, F Pantaleo, Davide Rossetti, Francesco Simula, M Sozzi, Laura Tosoratto, Piero Vicini
Publication date
2014/2/21
Journal
Journal of Instrumentation
Volume
9
Issue
02
Pages
C02023
Publisher
IOP Publishing
Description
NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities.
Total citations
2013201420152016201720182019202020212022202313833211232
Scholar articles