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An architecture is presented for hard-wired data-flow algorithms which is based on the transmission of arithmetic data one digit at a time serially, and performance of operations digit-serially on that data. It is shown that digit-serial computation gives rise to particularly efficient chip designs, and that choice of digit-size allows the user to match throughput requirements to specifications. Details of the implementation of the individual operators as a cell-library of silicon CMOS circuits are given and mention is made of the software environment (silicon compiler) which allows the rapid translation of algorithms to integrated circuits.< >