Authors
Sheung Lu, Bathiya Senevirathna, Marc Dandin, Elisabeth Smela, Pamela Abshire
Publication date
2018/5/27
Conference
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages
1-5
Publisher
IEEE
Description
Integrating CMOS sensor chips to allow for wet experimentation on lab-on-CMOS devices is a challenging task. In this paper we describe a chip packaging method that will allow for simple integration and handling of small integrated circuit (IC) chips. A chip is embedded in an epoxy handle wafer to allow for photolithographic processing. Electrical connections are provided by a sputter-deposited copper layer and an electroplated nickel layer. Passivation was performed using a second epoxy layer. The process was evaluated by packaging a capacitance sensor chip and performing live cell culture experiments with package cleaning and reuse. Results showed good structural reliability in three repeated experiments over five cumulative days, with no adverse effects on the viability of cells.
Total citations
201820192020202120222023132321
Scholar articles
S Lu, B Senevirathna, M Dandin, E Smela, P Abshire - 2018 IEEE International Symposium on Circuits and …, 2018