Analysis and characterization of inherent application resilience for approximate computing VK Chippa, ST Chakradhar, K Roy, A Raghunathan Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013 | 655 | 2013 |
A dynamically configurable coprocessor for convolutional neural networks S Chakradhar, M Sankaradas, V Jakkula, S Cadambi Proceedings of the 37th annual international symposium on Computer …, 2010 | 536 | 2010 |
Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain S Cadambi, A Majumdar, M Becchi, S Chakradhar, HP Graf US Patent 8,583,896, 2013 | 462 | 2013 |
Tarazu: optimizing mapreduce on heterogeneous clusters F Ahmad, ST Chakradhar, A Raghunathan, TN Vijaykumar ACM SIGARCH Computer Architecture News 40 (1), 61-74, 2012 | 369 | 2012 |
Quality programmable vector processors for approximate computing S Venkataramani, VK Chippa, ST Chakradhar, K Roy, A Raghunathan Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 355 | 2013 |
Approximate computing and the quest for computing efficiency S Venkataramani, ST Chakradhar, K Roy, A Raghunathan Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 339 | 2015 |
Tamper resistance mechanisms for secure embedded systems S Ravi, A Raghunathan, S Chakradhar 17th International Conference on VLSI Design. Proceedings., 605-611, 2004 | 327 | 2004 |
A massively parallel coprocessor for convolutional neural networks M Sankaradas, V Jakkula, S Cadambi, S Chakradhar, I Durdanovic, ... 2009 20th IEEE International Conference on Application-specific Systems …, 2009 | 322 | 2009 |
On-chip networks: A scalable, communication-centric embedded system design paradigm J Henkel, W Wolf, S Chakradhar 17th International Conference on VLSI Design. Proceedings., 845-851, 2004 | 270 | 2004 |
Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency VK Chippa, D Mohapatra, A Raghunathan, K Roy, ST Chakradhar Proceedings of the 47th Design Automation Conference, 555-560, 2010 | 244 | 2010 |
A transitive closure algorithm for test generation ST Chakradhar, VD Agrawal, SG Rothweiler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 232 | 1993 |
An exact algorithm for selecting partial scan flip-flops ST Chakradhar, A Balakrishnan, VD Agrawal Proceedings of the 31st annual Design Automation Conference, 81-86, 1994 | 219 | 1994 |
Supporting GPU sharing in cloud environments with a transparent runtime consolidation framework VT Ravi, M Becchi, G Agrawal, S Chakradhar Proceedings of the 20th international symposium on High performance …, 2011 | 188 | 2011 |
{ShuffleWatcher}: Shuffle-aware scheduling in multi-tenant {MapReduce} clusters F Ahmad, ST Chakradhar, A Raghunathan, TN Vijaykumar 2014 USENIX Annual Technical Conference (USENIX ATC 14), 1-13, 2014 | 180 | 2014 |
Dynamically configurable, multi-ported co-processor for convolutional neural networks S Chakradhar, M Sankaradas, VS Jakkula, S Cadambi US Patent 8,442,927, 2013 | 176 | 2013 |
Best-effort computing: Re-thinking parallel software and hardware ST Chakradhar, A Raghunathan Proceedings of the 47th Design Automation Conference, 865-870, 2010 | 165 | 2010 |
First-order versus second-order single-layer recurrent neural networks MW Goudreau, CL Giles, ST Chakradhar, D Chen IEEE Transactions on Neural Networks 5 (3), 511-513, 1994 | 150 | 1994 |
Optimizing memory efficiency for deep convolutional neural networks on GPUs C Li, Y Yang, M Feng, S Chakradhar, H Zhou SC'16: Proceedings of the International Conference for High Performance …, 2016 | 139 | 2016 |
A design methodology for application-specific networks-on-chip J Xu, W Wolf, J Henkel, S Chakradhar ACM Transactions on Embedded Computing Systems (TECS) 5 (2), 263-280, 2006 | 138 | 2006 |
Scalable effort hardware design VK Chippa, D Mohapatra, K Roy, ST Chakradhar, A Raghunathan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (9 …, 2014 | 135 | 2014 |