Sebastian Gomez Dominguez

Sebastian Gomez Dominguez

Estudiante
Verified email at prepauvm.com.mx
Cited by 28806
UVM
Sara Marconi

Sara Marconi

PhD student, University of Perugia; Doctoral Student, CERN
Verified email at cern.ch
Cited by 3107
VLSI design simulation and verification (SystemVerilog UVM) High Energy Physics applications
Clifford Cummings

Clifford Cummings

VP of Training, Paradigm Works, Inc.
Verified email at sunburst-design.com
Cited by 955
Verilog SystemVerilog UVM Synthesis
Khaled Salah, Ph.D, MBA, SMIEEE

Khaled Salah, Ph.D, MBA, SMIEEE

Siemens
Verified email at siemens.com
Cited by 873
IoT 3DIC Machine Learning UVM SoC
Sebastian Simon

Sebastian Simon

Infineon Technologies Dresden
Verified email at infineon.com
Cited by 350
Electrical Engineering Analog Verification Digital Verification Mixed-Signal UVM
Elia Conti

Elia Conti

Digital verification engineer, Kandou Bus, Lausanne (Switzerland)
Verified email at kandou.com
Cited by 242
Digital verification UVM VLSI
Tse-Chen Yeh

Tse-Chen Yeh

Engineer
Verified email at wdc.com
Cited by 197
QEMU SystemC SystemVerilog UVM
Tyler Allen

Tyler Allen

UNC Charlotte
Verified email at charlotte.edu
Cited by 189
HPC Performance GPU Virtual Memory UVM
Sameh El-Ashry

Sameh El-Ashry

Principal ASIC Design Verification Engineer, MSc, SMIEEE
Verified email at ieee.org
Cited by 151
Digital IC Verification UVM Coverage NoC SoC.
Srinivasan Venkataramanan

Srinivasan Venkataramanan

CEO
Verified email at verifworks.com
Cited by 132
Design Verification UVM Assertion Based Verification
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