| 34 An Asynchronous Microprocessor in Arsenide Gallium JA Tierno, AJ Martin, D Borkovic, TK Lee Logic and Architecture Synthesis, 330, 2016 | | 2016 |
| A 0.1 pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI Y Liu, PH Hsieh, S Kim, J Seo, R Montoye, L Chang, J Tierno, D Friedman 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 34 | 2013 |
| A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces J Tierno, A Rylyakov, S Rylov, M Singh, P Ampadu, S Nowick, ... 2002 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2002 | 10 | 2002 |
| A 1.4 pJ/bit, power-scalable 16× 12 Gb/s source-synchronous I/O with DFE receiver in 32 nm SOI CMOS technology TO Dickson, Y Liu, SV Rylov, A Agrawal, S Kim, PH Hsieh, JF Bulzacchelli, ... IEEE Journal of Solid-State Circuits 50 (8), 1917-1931, 2015 | 47 | 2015 |
| A 1.4-pJ/b, Power-Scalable 16x12-Gb/s Source-Synchronous I/O with DFE Receiver in 32nm SOI CMOS Technology CB Parker, L Shan, Y Kwark, J Tierno, DJ Friedman GEN 2 (C2Q), C2I, 0 | | |
| A 100-MIPS GaAs asynchronous microprocessor JA Tierno, AJ Martin, D Borkovic, TK Lee IEEE Design & Test of Computers 11 (2), 43-49, 1994 | 67 | 1994 |
| A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS A Agrawal, JF Bulzacchelli, TO Dickson, Y Liu, JA Tierno, DJ Friedman IEEE journal of solid-state circuits 47 (12), 3220-3231, 2012 | 115 | 2012 |
| A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels S Rylov, A Rylyakov, J Tierno, M Immediato, M Beakes, M Kapur, ... 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001 | 21 | 2001 |
| A 21.8–27.5 GHz PLL in 32nm SOI using Gm linearization to achieve− 130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier B Sadhu, MA Ferriss, JO Plouchart, AS Natarajan, AV Rylyakov, ... 2012 IEEE Radio Frequency Integrated Circuits Symposium, 75-78, 2012 | 15 | 2012 |
| A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS JO Plouchart, MA Ferriss, AS Natarajan, A Valdes-Garcia, B Sadhu, ... IEEE Transactions on Circuits and Systems I: Regular Papers 60 (8), 2009-2017, 2013 | 24 | 2013 |
| A 28 ghz hybrid pll in 32 nm soi cmos M Ferriss, A Rylyakov, JA Tierno, H Ainspan, DJ Friedman IEEE Journal of Solid-State Circuits 49 (4), 1027-1035, 2014 | 66 | 2014 |
| A 3.2 GS/s 4.55 b ENOB two-step subranging ADC in 45nm SOI CMOS JO Plouchart, MAT Sanduleanu, Z Toprak-Deniz, TJ Beukema, ... Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 8 | 2012 |
| A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons J Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ... 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 457 | 2011 |
| A 7-tap transverse analog-FIR filter in 0.12/spl mu/m CMOS for equalization of 10Gb/s fiber-optic data systems S Reynolds, P Pepeljugoski, J Schaub, J Tierno, D Beisser ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 57 | 2005 |
| A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation S Asaad, R Bellofatto, B Brezzo, C Haymes, M Kapur, B Parker, T Roewer, ... Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 94 | 2012 |
| A DPLL-based per core variable frequency clock generator for an eight-core POWER7™microprocessor J Tierno, A Rylyakov, D Friedman, A Chen, A Ciesla, T Diemoz, G English, ... 2010 Symposium on VLSI Circuits, 85-86, 2010 | 35 | 2010 |
| A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, JO Plouchart, AV Rylyakov, ... IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013 | 101 | 2013 |
| A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65nm CMOS AV Rylyakov, JA Tierno, DZ Turker, JO Plouchart, HA Ainspan, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 38 | 2008 |
| A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI JA Tierno, AV Rylyakov, DJ Friedman IEEE Journal of Solid-State Circuits 43 (1), 42-51, 2008 | 241 | 2008 |
| A wide power-supply range (0.5 V-to-1.3 V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI AV Rylyakov, JA Tierno, GJ English, D Friedman, M Meghelli 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 43 | 2007 |
Daniel FriedmanIBMVerified email at us.ibm.com