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Zebo Peng
Zebo Peng
Professor of Computer Systems, Linkoping University
Verified email at liu.se - Homepage
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11th International Symposium on System-Level Synthesis and Design (ISSS’98)........... AC-H. Wu and ND Dutt 469
P Eles, A Doboli, P Pop, Z Peng, S Yoo, K Choi, DS Ha, JH Hong, CH Tsai, ...
13th IEEE European Test Symposium (ETS'08)
P Girard, MS Reorda, Z Peng, C Landrault, C Metra
IEEE Computer Society, 2008
2008
A Behavioral-Level Testability Enhancement Technique
E Larsson, Z Peng
Compendium of Papers of the European Test Workshop, 1999
71999
A Board-Level Test Controller to Support a Hierarchical DFT Architecture
J Håkegård, G Carlsson, Z Peng
IEEE European Test Workshop, 1996
21996
A controller testability analysis and enhancement technique
X Gu, E Larsson, K Kuchinski, Z Peng
Proceedings European Design and Test Conference. ED & TC 97, 153-157, 1997
191997
A Design Framework for Dynamic Embedded Systems with Security Constraints
K Jiang, P Eles, Z Peng
SSoCC13, 2013
2013
A design representation for hardware/software co-synthesis
E Stoy, Z Peng
Proceedings of Twentieth Euromicro Conference. System Architecture and …, 1994
101994
A deterministic-path routing algorithm for tolerating many faults on very-large-scale network-on-chip
Y Zhang, X Hong, Z Chen, Z Peng, J Jiang
ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (1 …, 2020
92020
A deterministic-path routing algorithm for tolerating many faults on wafer-level NoC
Z Chen, Y Zhang, Z Peng, J Jiang
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019
122019
A formal methodology for automated synthesis of vlsi systems
Z Peng
(No Title), 1987
291987
A Formal Verification Approach for IP-based Designs.
D Karlsson, P Eles, Z Peng
FDL, 556-568, 2004
12004
A formal verification methodology for IP-based designs
D Karlsson, P Eles, Z Peng
Euromicro Symposium on Digital System Design, 2004. DSD 2004., 372-379, 2004
52004
A front end to a java based environment for the design of embedded systems
D Karlsson, P Eles, Z Peng
4th IEEE Design and Diagnosis of Electronic Circuit and Systems (DDECS), 71-78, 2001
72001
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
A Larsson, E Larsson, P Eles, Z Peng
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-6, 2007
62007
A heuristic for thermal-safe SoC test scheduling
Z He, Z Peng, P Eles
2007 IEEE International Test Conference, 1-10, 2007
412007
A heuristic for wiring-aware built-in self-test synthesis
AR Mohamed, Z Peng, P Eles
Euromicro Symposium on Digital System Design, 2004. DSD 2004., 408-415, 2004
2004
A hierarchical test generation technique for embedded systems
G Jervan, P Eles, Z Peng
Proc. Electronic Circuits and Systems Conference, 21-24, 1999
91999
A Horizontal Optimization Algorithm for Data Path
Z Peng
Institutionen för Datavetenskap, Universitetet och Tekniska Högskolan, 1988
1988
A horizontal optimization algorithm for data path/control synthesis
Z Peng
1988., IEEE International Symposium on Circuits and Systems, 239-242, 1988
11988
A hybrid BIST architecture and its optimization for SoC testing
G Jervan, Z Peng, R Ubar, H Kruus
Proceedings International Symposium on Quality Electronic Design, 273-279, 2002
432002
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