| “A 10-Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65-nm CMOS,” Deemed Best 2009 JSSC Paper JFB Friedman, TO Dickson, Y Liu, B Kim IEEE Solid-State Circuits Magazine, 55, 2011 | | 2011 |
| 2.5 D and 3D technology challenges and test vehicle demonstrations JU Knickerbocker, PS Andry, E Colgan, B Dang, T Dickson, X Gu, ... 2012 IEEE 62nd Electronic Components and Technology Conference, 1068-1076, 2012 | 120 | 2012 |
| 30-100-GHz inductors and transformers for millimeter-wave (Bi) CMOS integrated circuits S Voinigescu, TO Dickson, MA LaCroix, S Boret, D Gloria, R Beerkens IEEE, 2005 | | 2005 |
| 30-100-GHz inductors and transformers for millimeter-wave (Bi) CMOS integrated circuits TO Dickson, MA LaCroix, S Boret, D Gloria, R Beerkens, SP Voinigescu IEEE transactions on microwave theory and techniques 53 (1), 123-133, 2005 | 256 | 2005 |
| 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases TO Dickson, KIM Bongjin US Patent 9,876,667, 2018 | 1 | 2018 |
| 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases TO Dickson, KIM Bongjin US Patent 10,171,281, 2019 | 5 | 2019 |
| 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases TO Dickson, KIM Bongjin US Patent 9,674,025, 2017 | 28 | 2017 |
| 6.5 A 1.8 pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS TO Dickson, HA Ainspan, M Meghelli 2017 IEEE International Solid-State Circuits Conference (ISSCC), 118-119, 2017 | 45 | 2017 |
| A 1.4 pJ/bit, power-scalable 16× 12 Gb/s source-synchronous I/O with DFE receiver in 32 nm SOI CMOS technology TO Dickson, Y Liu, SV Rylov, A Agrawal, S Kim, PH Hsieh, JF Bulzacchelli, ... IEEE Journal of Solid-State Circuits 50 (8), 1917-1931, 2015 | 47 | 2015 |
| A 1.5 V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis P Westergaard, TO Dickson, SP Voinigescu Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat …, 2004 | 37 | 2004 |
| A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration TO Dickson, Y Liu, A Agrawal, JF Bulzacchelli, HA Ainspan, ... IEEE Journal of Solid-State Circuits 51 (8), 1744-1755, 2016 | 41 | 2016 |
| A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS Y Liu, B Kim, TO Dickson, JF Bulzacchelli, DJ Friedman International Solid State Circuits Conference, 2009 | 184 | 2009 |
| A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology TO Dickson, JF Bulzacchelli, DJ Friedman IEEE Journal of Solid-State Circuits 44 (4), 1298-1305, 2009 | 126 | 2009 |
| A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS Z Toprak-Deniz, JE Proesel, JF Bulzacchelli, HA Ainspan, TO Dickson, ... IEEE Journal of Solid-State Circuits 55 (1), 19-26, 2019 | 66 | 2019 |
| A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS A Agrawal, JF Bulzacchelli, TO Dickson, Y Liu, JA Tierno, DJ Friedman IEEE journal of solid-state circuits 47 (12), 3220-3231, 2012 | 115 | 2012 |
| A 2-GHz direct sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL T Chalvatzis, TO Dickson, SP Voinigescu 2007 IEEE Symposium on VLSI Circuits, 54-55, 2007 | 10 | 2007 |
| A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic S Voinigescu, TO Dickson, R Beerkens IEEE, 2005 | | 2005 |
| A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic TO Dickson, R Beerkens, SP Voinigescu IEEE Journal of Solid-State Circuits 40 (4), 994-1003, 2005 | 79 | 2005 |
| A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS JE Proesel, TO Dickson 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 206-207, 2011 | 47 | 2011 |
| A 32 Gb/s, 4.7 pJ/bit optical link with− 11.7 dBm sensitivity in 14-nm FinFET CMOS JE Proesel, Z Toprak-Deniz, A Cevrero, I Ozkaya, S Kim, DM Kuchta, ... IEEE Journal of Solid-State Circuits 53 (4), 1214-1226, 2017 | 68 | 2017 |
Jonathan ProeselNubis CommunicationsVerified email at nubis-communications.com
