| High-performance and robust spintronic/CNTFET-based binarized neural network hardware accelerator MT Nasab, A Amirany, MH Moaiyeri, K Jafari IEEE Transactions on Emerging Topics in Computing 11 (2), 527-533, 2022 | 20 | 2022 |
| Hybrid MTJ/CNTFET-based binary synapse and neuron for process-in-memory architecture MT Nasab, A Amirany, MH Moaiyeri, K Jafari IEEE Magnetics Letters 14, 1-5, 2023 | 11 | 2023 |
| High performance and low power spintronic binarized neural network hardware accelerator MT Nasab, A Amirany, MH Moaiyeri, K Jafari 2022 30th International Conference on Electrical Engineering (ICEE), 774-778, 2022 | 6 | 2022 |
| Radiation immune spintronic binary synapse and neuron for process-in-memory architecture MT Nasab, A Amirany, MH Moaiyeri, K Jafari IEEE Magnetics Letters, 2024 | 5 | 2024 |
| Low-Power Adiabatic/MTJ LIM-Based XNOR/XOR Synapse and Neuron for Binarized Neural Networks MT Nasab, H Thapliyal 2023 IEEE 23rd International Conference on Nanotechnology (NANO), 649-654, 2023 | 3 | 2023 |
| FinFET-based Low-Power Approximate Multiplier for Neural Network Hardware Accelerator F Baraati, MT Nasab, R Ghaderi, K Jafari 2022 Iranian International Conference on Microelectronics (IICM), 17-20, 2022 | 3 | 2022 |
| Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications W Yang, M Tanavardi Nasab, H Thapliyal Electronics 13 (7), 1309, 2024 | 1 | 2024 |
| Energy-Efficient Adiabatic MTJ/CMOS-Based CLB for Non-Volatile FPGA MT Nasab, W Yang, H Thapliyal 2024 IEEE 24th International Conference on Nanotechnology (NANO), 517-522, 2024 | | 2024 |
| Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures MT Nasab, A Amirany, MH Moaiyeri, K Jafari AEU-International Journal of Electronics and Communications 178, 155284, 2024 | | 2024 |
Kian JafariAssociate Professor at Faculty of Engineering, University of SherbrookeVerified email at usherbrooke.ca
