| Asymmetric mesh NoC topologies J Philip, S Kumar, E Norige, M Hassan, S Mitra US Patent 8,819,616, 2014 | 97 | 2014 |
| Asymmetric mesh NoC topologies J Philip, S Kumar, E Norige, M Hassan, S Mitra US Patent 8,819,611, 2014 | 95 | 2014 |
| Asymmetric mesh NoC topologies J Philip, S Kumar, E Norige, M Hassan, S Mitra US Patent 8,601,423, 2013 | 93 | 2013 |
| Automatic construction of deadlock free interconnects J Philip, S Kumar, E Norige, M Hassan, S Mitra US Patent 9,244,880, 2016 | 89 | 2016 |
| Heterogeneous channel capacities in an interconnect S Kumar, J Philip, E Norige, M Hassan, S Mitra US Patent 8,885,510, 2014 | 87 | 2014 |
| Combining associativity and cuckoo hashing J Philip, S Kumar, J Rowlands US Patent 9,223,711, 2015 | 63 | 2015 |
| Creating multiple NoC layers for isolation or avoiding NoC traffic congestion S Kumar, E Norige, J Philip, M Hassan, S Mitra, J Rowlands US Patent 9,130,856, 2015 | 57 | 2015 |
| Configurable router for a network on chip (NoC) J Philip, S Kumar US Patent 9,742,630, 2017 | 53 | 2017 |
| Supporting multicast in NOC interconnect S Kumar, E Norige, J Rowlands, J Philip US Patent 9,473,388, 2016 | 53 | 2016 |
| Multiple clock domains in NoC J Philip, J Rowlands, S Kumar US Patent 10,027,433, 2018 | 51 | 2018 |
| Supporting multicast in NoC interconnect S Kumar, E Norige, J Rowlands, J Philip US Patent 9,590,813, 2017 | 30 | 2017 |
| Hierarchical asymmetric mesh with virtual routers S Kumar, E Norige, J Philip, M Hassan, S Mitra, J Rowlands US Patent 9,253,085, 2016 | 29 | 2016 |
| Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification S Kumar, E Norige, J Philip, M Hassan, S Mitra, J Rowlands US Patent 9,009,648, 2015 | 23 | 2015 |
| Systems and methods for maintaining network-on-chip (noc) safety and reliability J Philip, J Rowlands, S Kumar US Patent App. 16/265,948, 2019 | 20 | 2019 |
| QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes S Kumar, E Norige, J Philip, M Hassan, S Mitra, J Rowlands US Patent 9,007,920, 2015 | 17 | 2015 |
| Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip J Philip, S Kumar US Patent 9,825,809, 2017 | 13 | 2017 |
| A fault modeling technique to test memory BIST algorithms R Venkatesh, S Kumar, J Philip, S Shukla Proceedings of the 2002 IEEE International Workshop on Memory Technology …, 2002 | 10 | 2002 |
| Interface virtualization and fast path for network on chip J Rowlands, J Philip, S Kumar, N Rao US Patent App. 15/829,749, 2018 | 6 | 2018 |
| Rule caching for packet classification support J Philip, M Taneja, R Rojas-Cessa 2008 IEEE Sarnoff Symposium, 1-5, 2008 | 6 | 2008 |
| Tagging and synchronization for fairness in NOC interconnects S Kumar, E Norige, J Philip, M Hassan, S Mitra, J Rowlands US Patent 9,185,026, 2015 | 5 | 2015 |
