Articles with public access mandates - Ritchie ZhaoLearn more
Available somewhere: 13
Accelerating binarized convolutional neural networks with software-programmable FPGAs
R Zhao, W Song, W Zhang, T Xing, JH Lin, M Srivastava, R Gupta, ...
Proceedings of the 2017 ACM/SIGDA international symposium on field …, 2017
Mandates: US National Science Foundation, US Department of Defense
Improving neural network quantization without retraining using outlier channel splitting
R Zhao, Y Hu, J Dotzel, C De Sa, Z Zhang
International conference on machine learning, 7543-7552, 2019
Mandates: US Department of Defense
Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs
Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
Mandates: US National Science Foundation, US Department of Defense
The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
Mandates: US National Science Foundation, US Department of Defense
A parallel bandit-based approach for autotuning FPGA compilation
C Xu, G Liu, R Zhao, S Yang, G Luo, Z Zhang
Proceedings of the 2017 ACM/SIGDA international symposium on field …, 2017
Mandates: US National Science Foundation, US Department of Defense, National Natural …
Dynamic hazard resolution for pipelining irregular loops in high-level synthesis
S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
Mandates: US National Science Foundation, US Department of Defense
Celerity: An open source RISC-V tiered accelerator fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
Mandates: US Department of Defense
Building efficient deep neural networks with unitary group convolutions
R Zhao, Y Hu, J Dotzel, CD Sa, Z Zhang
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2019
Mandates: US Department of Defense
Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
Mandates: US National Science Foundation, US Department of Defense
Enabling adaptive loop pipelining in high-level synthesis
S Dai, G Liu, R Zhao, Z Zhang
2017 51st Asilomar Conference on Signals, Systems, and Computers, 131-135, 2017
Mandates: US National Science Foundation, US Department of Defense
Improving high-level synthesis with decoupled data structure optimization
R Zhao, G Liu, S Srinath, C Batten, Z Zhang
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
Mandates: US National Science Foundation
Architecture and synthesis for area-efficient pipelining of irregular loop nests
G Liu, M Tan, S Dai, R Zhao, Z Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
Mandates: US National Science Foundation, US Department of Defense
Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm
TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ...
1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
Mandates: US National Science Foundation, US Department of Defense
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