| Scalable high-performance architecture for convolutional ternary neural networks on FPGA A Prost-Boucle, A Bourge, F Pétrot, H Alemdar, N Caldwell, V Leroy Field Programmable Logic and Applications (FPL), 2017 27th International …, 2017 | 96 | 2017 |
| Generating efficient context-switch capable circuits through autonomous design flow A Bourge, O Muller, F Rousseau ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (1), 1-23, 2016 | 31 | 2016 |
| High-efficiency convolutional ternary neural networks with custom adder trees and weight compression A Prost-Boucle, A Bourge, F Pétrot ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-24, 2018 | 29 | 2018 |
| Automatic high-level hardware checkpoint selection for reconfigurable systems A Bourge, O Muller, F Rousseau 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 17 | 2015 |
| Flexible, extensible, open-source and affordable FPGA-based traffic generator T Groléat, M Arzel, S Vaton, A Bourge, Y Le Balch, H Bougdal, ... Proceedings of the first edition workshop on High performance and …, 2013 | 11 | 2013 |
| Efficient Decompression of Binary Encoded Balanced Ternary Sequences O Muller, A Prost-Boucle, A Bourge, F Pétrot IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …, 2019 | 9 | 2019 |
| Efficient Decompression of Binary Encoded Balanced Ternary Sequences O Muller, A Prost-Boucle, A Bourge, F Pétrot IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …, 2019 | 9 | 2019 |
| HLS-based methodology for fast iterative development applied to Elliptic Curve arithmetic S Pontie, A Bourge, A Prost-Boucle, P Maistri, O Muller, R Leveugle, ... 2016 Euromicro Conference on Digital System Design (DSD), 511-518, 2016 | 6 | 2016 |
| Prototyping dynamic task migration on heterogeneous reconfigurable systems A Wicaksana, A Bourge, O Muller, A Sasongko, F Rousseau Proceedings of the 28th International Symposium on Rapid System Prototyping …, 2017 | 5 | 2017 |
| Changement de contexte matériel sur FPGA entre équipements reconfigurables et hétérogènes dans un environnement de calcul distribué. A Bourge Université Grenoble-Alpes, 2016 | 4 | 2016 |
| Demonstration of a context-switch method for heterogeneous reconfigurable systems A Wicaksana, A Bourge, O Muller, F Rousseau 2016 26th International Conference on Field Programmable Logic and …, 2016 | 4 | 2016 |
| Hardware-friendly AI algorithms: Ternary Neural Networks F Pétrot, A Prost-Boucle, A Bourge, LLA Porras, T Baumela, A Pinzari HiPEAC Computing Systems Week (HiPEAC 2021), 2021 | | 2021 |
| High-Throughput and High-Accuracy Classification with Convolutional Ternary Neural Networks F Pétrot, A Prost-Boucle, A Bourge International Workshop on Highly Efficient Neural Processing (HENP'2018), 2018 | | 2018 |
| High-Throughput Ternary CNN on FPGA: Low Level Optimizations and Compression F Pétrot, A Prost-Boucle, A Bourge 18th International Forum on MPSoC (MPSoC'2018), 2018 | | 2018 |
| Flot de conception automatique pour circuits commutables A Bourge, O Muller, F Rousseau Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2016), 2016 | | 2016 |
| A Novel Method for Enabling FPGA Context-Switch A Bourge, O Muller, F Rousseau Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | | 2015 |
| La synthèse de haut niveau au service du changement de contexte matériel. A Bourge, O Muller, F Rousseau Colloque National GDR SoC-SiP, 2015 | | 2015 |
| Méthode de sélection de checkpoint matériel avec outil de synthèse de haut niveau A Bourge, A Ghiti, O Muller, F Rousseau Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14), 4, 2014 | | 2014 |
| Efficient Decompression of Binary Encoded Balanced Ternary Sequences O Muller, A Prost-Boucle, A Bourge, F Pétrot networks 7, 8, 0 | | |
Frédéric PétrotTIMA Lab, Université Grenoble Alpes, Grenoble Institute of EngineeringVerified email at univ-grenoble-alpes.fr
