| 23.8 A 40Gb/s 14mW CMOS wireline receiver A Manian, B Razavi 2016 IEEE International Solid-State Circuits Conference (ISSCC), 412-414, 2016 | 31* | 2016 |
| A 40-Gb/s 14-mW CMOS wireline receiver A Manian, B Razavi IEEE Journal of Solid-State Circuits 52 (9), 2407-2421, 2017 | 30 | 2017 |
| An 80-Gb/s 44-mW wireline PAM4 transmitter Y Chang, A Manian, L Kong, B Razavi IEEE Journal of Solid-State Circuits 53 (8), 2214-2226, 2018 | 28 | 2018 |
| A 40-Gb/s 9.2-mW CMOS equalizer A Manian, B Razavi 2015 Symposium on VLSI Circuits (VLSI Circuits), C226-C227, 2015 | 13 | 2015 |
| A simultaneous bidirectional single-ended coaxial link with 24-Gb/s forward and 312.5-Mb/s back channels A Manian, A Rane, Y Koh, HK Nat, M Lu IEEE Journal of Solid-State Circuits 56 (3), 972-987, 2020 | 8 | 2020 |
| Frequency/phase lock detector for clock and data recovery circuits A Manian, MG Vrazel US Patent 10,644,868, 2020 | 7 | 2020 |
| A 32-mw 40-gb/s cmos nrz transmitter Y Chang, A Manian, L Kong, B Razavi 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018 | 7 | 2018 |
| A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply A Manian, B Razavi Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 7 | 2014 |
| Loss of lock detector A Manian, R Gupta US Patent 10,236,897, 2019 | 3 | 2019 |
| Low-Power Techniques for CMOS Wireline Receivers A Manian University of California, Los Angeles, 2016 | 3 | 2016 |
| Clockless delay adaptation loop for random data A Manian US Patent 10,897,245, 2021 | 2 | 2021 |
| Error sampler circuit A Manian, NS Poduval, RNO Ribeiro US Patent 11,575,546, 2023 | 1 | 2023 |
| Error sampler circuit A Manian, NS Poduval, RNO Ribeiro US Patent App. 18/419,653, 2024 | | 2024 |
| Receiver with pre-cursor intersymbol interference mitigation A Manian, AR ZAMIR, Y Tang, R Gupta, MG Vrazel US Patent App. 18/309,587, 2024 | | 2024 |
| Methods and apparatus to perform cml-to-cmos deserialization NS Poduval, A Manian, RNO Ribeiro US Patent App. 18/539,381, 2024 | | 2024 |
| Error sampler circuit A Manian, NS Poduval, RNO Ribeiro US Patent 11,916,703, 2024 | | 2024 |
| Methods and apparatus to perform CML-to-CMOS deserialization NS Poduval, A Manian, RNO Ribeiro US Patent 11,888,478, 2024 | | 2024 |
| Sample-and-hold-based retimer supporting link training A Manian, A Rane, AK Vijayan US Patent 11,743,080, 2023 | | 2023 |
| Equalization adaptation engine assisted baseline wander correction of data A Manian, A Rane US Patent App. 17/588,706, 2023 | | 2023 |
| Coarse equalizer adaptation and rate detection for high-speed retimers R Gupta, A Manian US Patent 11,621,715, 2023 | | 2023 |
Behzad RazaviProfessor of Electrical Engineering, UCLAVerified email at ee.ucla.edu
