| Efficient context saving and restoring in a multi-tasking computing system environment SP Song, MA Mohamed, H Park, LT Nguyen, JR Van Aken, A Forin, ... US Patent 6,061,711, 2000 | 152 | 2000 |
| Cache control unit with a cache request transaction-oriented protocol YP Pai, LT Nguyen US Patent 5,860,158, 1999 | 118 | 1999 |
| Superscalar risc instruction scheduling S Garg, KR Iadonato, LT Nguyen, J Wang US Patent 5,497,499, 1996 | 98 | 1996 |
| High-performance, superscalar-based computer system with out-of-order instruction execution LT Nguyen, DJ Lentz, Y Miyayama, S Garg, Y Hagiwara, J Wang, TL Lau, ... US Patent 5,539,911, 1996 | 95 | 1996 |
| RISC microprocessor architecture implementing multiple typed register sets S Garg, DJ Lentz, LT Nguyen, SL Chen US Patent 5,560,035, 1996 | 80 | 1996 |
| RISC microprocessor architecture implementing multiple typed register sets S Garg, DJ Lentz, LT Nguyen, SL Chen US Patent 5,493,687, 1996 | 79 | 1996 |
| Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor B Coon, Y Miyayama, LT Nguyen, J Wang US Patent 5,546,552, 1996 | 67 | 1996 |
| RISC microprocessor architecture implementing fast trap and exception state LT Nguyen, DJ Lentz, Y Miyayama, S Garg, Y Hagiwara, J Wang, Q Trang US Patent 5,448,705, 1995 | 65 | 1995 |
| Semiconductor floor plan for a register renaming circuit KR Iadonato, LT Nguyen US Patent 5,371,684, 1994 | 55 | 1994 |
| High-performance, superscalar-based computer system with out-of-order instruction execution DJ Lentz, Y Miyayama, S Garg, Y Hagiwara, J Wang, TL Lau, SS Wang, ... US Patent 6,948,052, 2005 | 52 | 2005 |
| Methods and apparatus for processing video data C Reader, JC Son, A Qureshi, L Nguyen, M Frederiksen, T Lu US Patent 6,192,073, 2001 | 49 | 2001 |
| RISC microprocessor architecture implementing fast trap and exception state LT Nguyen, DJ Lentz, Y Miyayama, S Garg, Y Hagiwara, J Wang, Q Trang US Patent 5,481,685, 1996 | 47 | 1996 |
| System and method for handling load and/or store operations in a superscalar microprocessor CS Brashears, J Wang, DJ Lentz, Y Miyayama, S Garg, Y Hagiwara, ... US Patent 6,965,987, 2005 | 44 | 2005 |
| Superscalar RISC instruction scheduling S Garg, KR Iadonato, J Wang US Patent 7,051,187, 2006 | 41 | 2006 |
| High-performance, superscalar-based computer system with out-of-order instruction execution DJ Lentz, Y Miyayama, S Garg, Y Hagiwara, J Wang, TL Lau, SS Wang, ... US Patent 7,739,482, 2010 | 38 | 2010 |
| System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture SP Song, MA Mohamed, H Park, L Nguyen US Patent 6,003,129, 1999 | 38 | 1999 |
| Parallel multiplier that supports multiple numbers with different bit lengths CS Kim, LT Nguyen, RS Wong US Patent 5,943,250, 1999 | 37 | 1999 |
| Microprocessor architecture capable of supporting multiple heterogeneous processors DJ Lentz, Y Hagiwara, TL Lau, CL Tang US Patent 6,954,844, 2005 | 36 | 2005 |
| Integrated circuit device implemented using a plurality of partially defective integrated circuit chips CM Lin, WY Ho, LT Nguyen US Patent 5,581,562, 1996 | 36 | 1996 |
| Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units DJ Lentz, J Wang, T Deosaran, LM Young, KC Yap, LT Nguyen, ... US Patent 5,564,117, 1996 | 34 | 1996 |
