| Design structures for high-voltage integrated circuits MJ Abou-Khalil, RJ Gauthier Jr, TC Lee, J Li, CS Putnam, S Mitra US Patent 7,786,535, 2010 | 240 | 2010 |
| A 7nm CMOS technology platform for mobile and high performance compute application S Narasimha, B Jagannathan, A Ogino, D Jaeger, B Greene, C Sheraw, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.5. 1-29.5. 4, 2017 | 66 | 2017 |
| Investigation of voltage overshoots in diode triggered silicon controlled rectifiers (DTSCRs) under very fast transmission line pulsing (VFTLP) R Gauthier, M Abou-Khalil, K Chatty, S Mitra, J Li 2009 31st EOS/ESD Symposium, 1-10, 2009 | 63 | 2009 |
| Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection J Li, R Gauthier, S Mitra, C Putnam, K Chatty, R Halbach, C Seguin 2006 Electrical Overstress/Electrostatic Discharge Symposium, 179-185, 2006 | 45 | 2006 |
| Deep-level transient spectroscopy study on double implanted n+–p and p+–n 4H-SiC diodes S Mitra, MV Rao, N Papanicolaou, KA Jones, M Derenge, OW Holland, ... Journal of applied physics 95 (1), 69-75, 2004 | 41 | 2004 |
| Semiconductor device heat dissipation structure MJ Abou-Khalil, RJ Gauthier Jr, TC Lee, J Li, S Mitra, CS Putnam US Patent 8,421,128, 2013 | 34 | 2013 |
| Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs R Mishra, DE Ioannou, S Mitra, R Gauthier IEEE electron device letters 29 (3), 262-264, 2008 | 34 | 2008 |
| Double gate (dg) soi ratioed logic with intrinsically on symmetric dg-mosfet load DE Ioannou, S Mitra, A Salman US Patent 7,180,135, 2007 | 34 | 2007 |
| Vertical current controlled silicon on insulator (SOI) device such as a silicon controlled rectifier and method of forming vertical SOI current controlled devices RJ Gauthier Jr, J Li, S Mitra, MA Mousa, CS Putnam US Patent 8,815,654, 2014 | 32 | 2014 |
| Fin contacted electrostatic discharge (ESD) devices with improved heat distribution JB Campi, RJ Gauthier Jr, R Mishra, S Mitra, M Muhammad US Patent 9,236,374, 2016 | 28 | 2016 |
| Gate-all-around fin device JB Campi, RJ Gauthier Jr, R Mishra, S Mitra, M Muhammad US Patent 9,397,163, 2016 | 27 | 2016 |
| RC-triggered semiconductor controlled rectifier for ESD protection of signal pads MJ Abou-Khalil, RJ Gauthier Jr, TC Lee, J Li, S Mitra, CS Putnam US Patent 8,891,212, 2014 | 26 | 2014 |
| Gate-all-around fin device JB Campi, RJ Gauthier Jr, R Mishra, S Mitra, M Muhammad US Patent 9,281,379, 2016 | 24 | 2016 |
| FinFET device technology with LDMOS structures for high voltage operations JB Campi, RJ Gauthier Jr, J Li, R Mishra, S Mitra, M Muhammad US Patent 9,041,127, 2015 | 24 | 2015 |
| Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology RJ Gauthier Jr, J Li, S Mitra US Patent 7,943,438, 2011 | 24 | 2011 |
| Apparatus and method for improved triggering and leakage current control of ESD clamping devices RJ Gauthier Jr, J Li, S Mitra, CS Putnam US Patent 7,274,546, 2007 | 23 | 2007 |
| Comprehensive study of ESD design window scaling down to 7nm technology node A Dong, J Xiong, S Mitra, W Liang, R Gauthier, A Loiseau 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 1-8, 2018 | 22 | 2018 |
| Attosecond-controlled photoemission from metal nanowire tips in the few-electron regime B Ahn, J Schötz, M Kang, WA Okell, S Mitra, B Förg, S Zherebtsov, ... Apl Photonics 2 (3), 2017 | 21 | 2017 |
| Gate-all-around fin device JB Campi, RJ Gauthier Jr, R Mishra, S Mitra, M Muhammad US Patent 9,590,108, 2017 | 19 | 2017 |
| Series-connected nanowire structures RJ Gauthier Jr, TB Hook, S Mitra US Patent 9,431,388, 2016 | 19 | 2016 |
Dimitris IoannouProfessor of Electrical Engineering, George Mason UniversityVerified email at gmu.edu