Event-Based Control and Signal Processing J Lunze, CG Cassandras, M Miskowicz, R Obermaisser, W Lang, ... CRC Press, 2016 | 247* | 2016 |
Energy-efficient hybrid analog/digital approximate computation in continuous time N Guo, Y Huang, T Mai, S Patil, C Cao, M Seok, S Sethumadhavan, ... IEEE Journal of Solid-State Circuits 51 (7), 1514-1524, 2016 | 98 | 2016 |
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving− 164-dBFS/Hz NSD H Shibata, V Kozlov, Z Ji, A Ganesan, H Zhu, D Paterson, J Zhao, S Patil, ... IEEE Journal of Solid-State Circuits 52 (12), 3219-3234, 2017 | 62 | 2017 |
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter H Shibata, G Taylor, B Schell, V Kozlov, S Patil, D Paterson, A Ganesan, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 260-262, 2020 | 46 | 2020 |
Derivative Level-Crossing Sampling P Martínez-Nuevo, S Patil, Y Tsividis IEEE Transactions on Circuits and Systems II: Express Briefs 62 (1), 11-15, 2015 | 36 | 2015 |
A 3–10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC S Patil, A Ratiu, D Morche, Y Tsividis IEEE Journal of Solid-State Circuits 51 (4), 908-918, 2016 | 26 | 2016 |
Continuous-time hybrid computation with programmable nonlinearities N Guo, Y Huang, T Mai, S Patil, C Cao, M Seok, S Sethumadhavan, ... European Solid-State Circuits Conference (ESSCIRC), ESSCIRC, 279-282, 2015 | 24 | 2015 |
A 3–10fJ/conv-step 0.0032 mm 2 error-shaping alias-free asynchronous ADC S Patil, A Ratiu, D Morche, Y Tsividis 2015 Symposium on VLSI Circuits (VLSI Circuits), C160-C161, 2015 | 11 | 2015 |
Digital processing of signals produced by voltage-controlled-oscillator-based continuous-time ADCs S Patil, Y Tsividis 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1046-1049, 2016 | 8 | 2016 |
Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays S Patil, SG Rao, Y Chen, Y Tsividis IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 1017-1030, 2019 | 6 | 2019 |
Blocker tolerance in continuous-time residue generating analog-to-digital converters SP Patil, H Shibata, Y Dong, DN Alldred, F Murden, LA Singer US Patent 10,187,075, 2019 | 6 | 2019 |
Reducing residue signals in analog-to-digital converters SP PATIL, H Shibata, WW Yang, DN ALLDRED, Y Dong, G Manganaro, ... US Patent 10,181,860, 2019 | 6 | 2019 |
A 6.4-GS/s 1-GHz BW continuous-time pipelined ADC with time-interleaved sub-ADC-DAC achieving 61.7-dB SNDR in 16-nm FinFET R Mittal, H Shibata, S Patil, E Krommenhoek, P Shrestha, G Manganaro, ... IEEE Journal of Solid-State Circuits, 2023 | 5 | 2023 |
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs MW Ismail, H Shibata, Z Li, S Patil, TC Carusone IEEE Transactions on Circuits and Systems I: Regular Papers 69 (12), 4731-4740, 2022 | 5 | 2022 |
Event-Based Data Acquisition and Digital Signal Processing in Continuous Time Y Tsividis, M Kurchuk, P Martinez-Nuevo, SM Nowick, S Patil, B Schell, ... Event-Based Control and Signal Processing, 253-278, 2015 | 5 | 2015 |
Digital estimation of transfer functions in continuous-time analog-to-digital converters SP Patil, DW Paterson, PM Shrestha, A Ganesan, Y Yin, Z Li, V Kozlov, ... US Patent 11,218,158, 2022 | 3 | 2022 |
Continuous time ADC and filter D Morche, A Ratiu, SP Patil, Y Tsividis US Patent 9,344,107, 2016 | 3 | 2016 |
Systems and methods for implementing error-shaping alias-free asynchronous flipping analog to digital conversion SP Patil, Y Tsividis, D Morche, A Ratiu US Patent 9,300,315, 2016 | 3 | 2016 |
Systems and methods for derivative level-crossing sampling SP Patil, Y Tsividis, PM NUEVO US Patent 9,071,257, 2015 | 3 | 2015 |
High-pass shaped dither in continuous-time residue generation systems for analog-to-digital converters V Kozlov, DW Paterson, SP Patil, H Shibata US Patent 11,652,491, 2023 | 2 | 2023 |