Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique SJ Doh, SW Rhee, JP Kim, JH Lee, J Lee, YS Kim US Patent App. 11/329,696, 2006 | 501 | 2006 |
Dielectric structures having high dielectric constants, and non-volatile semiconductor memory devices having the dielectric structures JC Lee, S Kim, Y Kim, C Yoo, G Nam, YG Park, JH Choi, J Yeo, HJ Lim, ... US Patent 7,482,677, 2009 | 155 | 2009 |
Semiconductor devices having different gate dielectrics and methods for manufacturing the same J Lee, H Kang, YS Kim, SJ Doh, HS Jung US Patent App. 10/930,943, 2005 | 125 | 2005 |
Method of fabricating high-k dielectric layer having reduced impurity HS Jung, J Lee, HJ Lim, JE Park, YS Kim, JH Yang US Patent 7,396,777, 2008 | 84 | 2008 |
Post thermal treatment methods of forming high dielectric layers in integrated circuit devices HS Jung, N Lee, J Lee, YS Kim US Patent 6,875,678, 2005 | 73 | 2005 |
Method of fabricating gate of semiconductor device using oxygen-free ashing process HS Jung, C Lee, J Lee, SK Han, YS Kim US Patent App. 11/699,784, 2007 | 64 | 2007 |
Method of fabricating metal silicate layer using atomic layer deposition technique YS Kim, JP Kim, HJ Lim, JE Park, HS Jung, J Lee, JH Yang US Patent 7,651,729, 2010 | 62 | 2010 |
Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same HJ Lim, J Lee, HS Jung, YS Kim, MJ Kim US Patent 7,547,951, 2009 | 57 | 2009 |
Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric HS Jung, YS Kim, JP Kim, JH Lee, JH Lee, NI Lee, HK Kang, KP Suh, ... Digest. International Electron Devices Meeting,, 853-856, 2002 | 52 | 2002 |
A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control HS Jung, JH Lee, SK Han, YS Kim, HJ Lim, MJ Kim, SJ Doh, MY Yu, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 232-233, 2005 | 45 | 2005 |
Mass production worthy HfO/sub 2/-Al/sub 2/O/sub 3/laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs JH Lee, JP Kim, JH Lee, YS Kim, HS Jung, NI Lee, HK Kang, KP Suh, ... Digest. International Electron Devices Meeting,, 221-224, 2002 | 43 | 2002 |
Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications CB Oh, HS Kang, HJ Ryu, MH Oh, HS Jung, YS Kim, JH He, NI Lee, ... Digest. International Electron Devices Meeting,, 423-426, 2002 | 35 | 2002 |
Semiconductor devices having different gate dielectrics and methods for manufacturing the same J Lee, H Kang, YS Kim, SJ Doh, HS Jung US Patent 7,586,159, 2009 | 24 | 2009 |
Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO (N) high-k gate dielectrics SJ Doh, HS Jung, YS Kim, HJ Lim, JP Kim, JH Lee, JH Lee, NI Lee, ... IEEE International Electron Devices Meeting 2003, 38.7. 1-38.7. 4, 2003 | 24 | 2003 |
Semiconductor devices having different gate dielectric layers and methods of manufacturing the same HS Jung, J Lee, HJ Lim, YS Kim US Patent App. 11/432,717, 2007 | 22 | 2007 |
Semiconductor device including gate dielectric layer formed of high dielectric alloy and method of fabricating the same HS Jung, J Lee, SJ Doh, YS Kim US Patent App. 10/989,200, 2005 | 20 | 2005 |
Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices SJ Doh, HS Jung, N Lee, J Lee, YS Kim US Patent 7,037,863, 2006 | 17 | 2006 |
Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices SJ Doh, HS Jung, N Lee, J Lee, YS Kim US Patent 7,494,940, 2009 | 15 | 2009 |
Poly-Si gate CMOSFETs with HfO/sub 2/-Al/sub 2/O/sub 3/laminate gate dielectric for low power applications JH Lee, YS Kim, HS Jung, JH Lee, NI Lee, HK Kang, JH Ku, HS Kang, ... 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002 | 15 | 2002 |
ALD ANALYSES OF HfC1,+ O3 AND HfCl+ H₂O BY MASS SPECTROSCOPY MS Kim, S Rogers, YS Kim, JH Lee, HK Kang Advanced Gate Stack, Source/drain and Channel Engineering for Si-based CMOS …, 2005 | 14 | 2005 |