| Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators X Yang, M Gao, Q Liu, J Setter, J Pu, A Nayak, S Bell, K Cao, H Ha, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 257 | 2020 |
| DNN dataflow choice is overrated X Yang, M Gao, J Pu, A Nayak, Q Liu, SE Bell, JO Setter, K Cao, H Ha, ... arXiv preprint arXiv:1809.04070, 2018 | 111 | 2018 |
| Creating an Agile Hardware Design Flow R Bahr, C Barrett, N Bhagdikar, A Carsello, R Daly, C Donovick, D Durst, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 31 | 2020 |
| Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra A Carsello, K Feng, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 23 | 2022 |
| Aha: An agile approach to the design of coarse-grained reconfigurable accelerators and compilers K Koul, J Melchert, K Sreedhar, L Truong, G Nyengele, K Zhang, Q Liu, ... ACM Transactions on Embedded Computing Systems 22 (2), 1-34, 2023 | 19 | 2023 |
| A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs A Nayak, K Zhang, R Setaluri, A Carsello, M Mann, S Richardson, R Bahr, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 846-851, 2020 | 10 | 2020 |
| Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains A Nayak, K Zhang, R Setaluri, A Carsello, M Mann, C Torng, ... ACM Transactions on Reconfigurable Technology and Systems 16 (2), 1-28, 2023 | 4 | 2023 |
| mflowgen: A modular flow generator and ecosystem for community-driven physical design A Carsello, J Thomas, A Nayak, PH Chen, M Horowitz, P Raina, C Torng Proceedings of the 59th ACM/IEEE Design Automation Conference, 1339-1342, 2022 | 4 | 2022 |
| Enabling Reusable Physical Design Flows with Modular Flow Generators A Carsello, J Thomas, A Nayak, PH Chen, M Horowitz, P Raina, C Torng arXiv preprint arXiv:2111.14535, 2021 | 3 | 2021 |
| Extraction of Structural Regularity for Random Logic Netlists CP Sotiriou, N Sketopoulos, A Nayak, P Penzes 2019 Panhellenic Conference on Electronics & Telecommunications (PACET), 1-7, 2019 | 3 | 2019 |
| Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration K Feng, A Carsello, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Hot Chips 34 Symposium (HCS), 1-30, 2022 | 2 | 2022 |
| Creating an agile hardware flow AHA Stanford, AH Center 2019 IEEE Hot Chips 31, 2019 | 1 | 2019 |
| Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra K Feng, T Kong, K Koul, J Melchert, A Carsello, Q Liu, G Nyengele, ... IEEE Journal of Solid-State Circuits, 2023 | | 2023 |
| On-device ML for 5G NR Modems A Nayak Sixth Conference on Machine Learning and Systems (MLSys 2023), 2023 | | 2023 |
| Improving Energy Efficiency for CGRA Architectures A Nayak Stanford University, 2023 | | 2023 |
| Interstellar X Yang, M Gao, Q Liu, J Setter, J Pu, A Nayak, S Bell, K Cao, H Ha, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | | 2020 |
| Power-density-based clock cell spacing A Nayak, DA Kidd, PI Penzes US Patent 9,824,174, 2017 | | 2017 |
