| Cobalt-containing conductive layers for control gate electrodes in a memory structure RS Makala, R Sharangpani, K Sateesh, G Mizuno, N Takeguchi, ... US Patent 10,128,261, 2018 | 141 | 2018 |
| Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks Z Lu, K Sateesh, J Kai, RS Makala, YS Lee, J Pachamuthu, J Alsmeier, ... US Patent 9,449,982, 2016 | 110 | 2016 |
| The crystalline to amorphous transition in PEO-based composite electrolytes: role of lithium salts B Kumar, SJ Rodrigues, S Koka Electrochimica Acta 47 (25), 4125-4131, 2002 | 81 | 2002 |
| Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure R Sharangpani, K Sateesh, RS Makala, S Peri, S Kanakamedala US Patent 9,659,955, 2017 | 72 | 2017 |
| Three-dimensional memory structure with multi-component contact via structure and method of making thereof S Peri, K Sateesh, RS Makala, R Sharangpani, M Baenninger, ... US Patent 9,698,152, 2017 | 69 | 2017 |
| Selective blocking dielectric formation in a three-dimensional memory structure RS Makala, R Sharangpani, SK Kanakamedala, X Liang, G Matamis, ... US Patent 9,484,357, 2016 | 64 | 2016 |
| Three-dimensional memory devices containing memory block bridges Z Lu, J Alsmeier, D Mao, W Shi, K Sateesh, RS Makala, G Matamis, ... US Patent 9,679,906, 2017 | 55 | 2017 |
| Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices R Sharangpani, K Sateesh, RS Makala, S Ranganathan, M Juanitas, ... US Patent 9,613,977, 2017 | 51 | 2017 |
| Performance evaluation on the weathering resistance of two USAF coating systems (standard 85285 topcoat versus fluorinated APC topcoat) via electrochemical impedance spectroscopy A Shi, S Koka, J Ullett Progress in organic coatings 52 (3), 196-209, 2005 | 51 | 2005 |
| Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure S Peri, K Sateesh, RS Makala US Patent 9,646,975, 2017 | 40 | 2017 |
| Ruthenium nucleation layer for control gate electrodes in a memory structure R Sharangpani, RS Makala, K Sateesh, G Matamis US Patent 9,496,419, 2016 | 38 | 2016 |
| Molybdenum-containing conductive layers for control gate electrodes in a memory structure S Peri, RS Makala, K Sateesh, YS Lee, J Alsmeier, G Matamis US Patent 9,780,182, 2017 | 37 | 2017 |
| Fluorine-free word lines for three-dimensional memory devices R Sharangpani, RS Makala, K Sateesh, G Matamis US Patent 9,397,046, 2016 | 37 | 2016 |
| Memory device containing cobalt silicide control gate electrodes and method of making thereof RS Makala, K Sateesh, Z Lu, S Peri, R Sharangpani US Patent 9,842,907, 2017 | 36 | 2017 |
| Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer K Sateesh, S Kanakamedala, RS Makala, R Sharangpani, Y Zhang, ... US Patent 9,478,558, 2016 | 35 | 2016 |
| Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure R Sharangpani, RS Makala, K Sateesh, T Kubo, J Ariyoshi, G Matamis US Patent 9,524,977, 2016 | 34 | 2016 |
| Three-dimensional memory devices having a shaped epitaxial channel portion and method of making thereof J Pachamuthu, K Sateesh, RS Makala, S Peri US Patent 9,754,958, 2017 | 31 | 2017 |
| Metal word lines for three dimensional memory devices R Sharangpani, RS Makala, SK Kanakamedala, K Sateesh, YS Lee, ... US Patent 9,570,455, 2017 | 31 | 2017 |
| Three dimensional NAND device and method of making thereof K Sateesh, S Kanakamedala, Y Zhang, RS Makala, R Sharangpani, ... US Patent 9,236,396, 2016 | 31 | 2016 |
| Method of making a three dimensional NAND device M Tsutsumi, S Fujino, K Sateesh, S Kanakamedala, Y Zhang, RS Makala, ... US Patent 9,305,849, 2016 | 27 | 2016 |
