| A bias-dependent single-event compact model implemented into BSIM4 and a 90 nm CMOS process design kit JS Kauppila, AL Sternberg, ML Alles, AM Francis, J Holmes, OA Amusan, ... IEEE Transactions on nuclear Science 56 (6), 3152-3157, 2009 | 198 | 2009 |
| Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance MP King, X Wu, M Eller, S Samavedam, MR Shaneyfelt, AI Silva, ... IEEE Transactions on Nuclear Science 64 (1), 285-292, 2016 | 81 | 2016 |
| A comparison of the SEU response of planar and FinFET D flip-flops at advanced technology nodes P Nsengiyumva, DR Ball, JS Kauppila, N Tam, M McCurdy, WT Holman, ... IEEE Transactions on Nuclear Science 63 (1), 266-272, 2016 | 74 | 2016 |
| On-chip measurement of single-event transients in a 45 nm silicon-on-insulator technology TD Loveless, JS Kauppila, S Jagannathan, DR Ball, JD Rowe, ... IEEE Transactions on Nuclear Science 59 (6), 2748-2755, 2012 | 59 | 2012 |
| Analysis of bulk FinFET structural effects on single-event cross sections P Nsengiyumva, LW Massengill, ML Alles, BL Bhuva, DR Ball, ... IEEE Transactions on Nuclear Science 64 (1), 441-448, 2016 | 58 | 2016 |
| Radiation hardness of fdsoi and finfet technologies ML Alles, RD Schrimpf, RA Reed, LW Massengill, RA Weller, ... IEEE 2011 International SOI Conference, 1-2, 2011 | 53 | 2011 |
| Estimating Single-Event Logic Cross Sections in Advanced Technologies RC Harrington, JS Kauppila, KM Warren, YP Chen, JA Maharrey, ... IEEE Transactions on Nuclear Science 64 (8), 2115-2121, 2017 | 40 | 2017 |
| Impact of process variations on SRAM single event upsets AV Kauppila, BL Bhuva, JS Kauppila, LW Massengill, WT Holman IEEE Transactions on Nuclear Science 58 (3), 834-839, 2011 | 40 | 2011 |
| Utilizing device stacking for area efficient hardened SOI flip-flop designs JS Kauppila, TD Loveless, RC Quinn, JA Maharrey, ML Alles, ... 2014 IEEE International Reliability Physics Symposium, SE. 4.1-SE. 4.7, 2014 | 39 | 2014 |
| Circuit-level layout-aware single-event sensitive-area analysis of 40-nm bulk CMOS flip-flops using compact modeling JS Kauppila, TD Haeffner, DR Ball, AV Kauppila, TD Loveless, ... IEEE Transactions on Nuclear Science 58 (6), 2680-2686, 2011 | 37 | 2011 |
| Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies H Zhang, H Jiang, TR Assis, DR Ball, K Ni, JS Kauppila, RD Schrimpf, ... 2016 IEEE International Reliability Physics Symposium (IRPS), 5C-3-1-5C-3-5, 2016 | 35 | 2016 |
| Angular effects on single-event mechanisms in bulk FinFET technologies P Nsengiyumva, LW Massengill, JS Kauppila, JA Maharrey, ... IEEE Transactions on Nuclear Science 65 (1), 223-230, 2017 | 33 | 2017 |
| Evaluation of SEU performance of 28-nm FDSOI flip-flop designs HB Wang, JS Kauppila, K Lilja, M Bounasser, L Chen, M Newton, YQ Li, ... IEEE Transactions on Nuclear Science 64 (1), 367-373, 2016 | 33 | 2016 |
| Effect of device variants in 32 nm and 45 nm SOI on SET pulse distributions JA Maharrey, RC Quinn, TD Loveless, JS Kauppila, S Jagannathan, ... IEEE Transactions on Nuclear Science 60 (6), 4399-4404, 2013 | 33 | 2013 |
| Single-event-hardened CMOS operational amplifier design RW Blaine, NM Atkinson, JS Kauppila, TD Loveless, SE Armstrong, ... IEEE Transactions on Nuclear Science 59 (4), 803-810, 2012 | 33 | 2012 |
| RHBD bias circuits utilizing sensitive node active charge cancellation RW Blaine, SE Armstrong, JS Kauppila, NM Atkinson, BD Olson, ... IEEE Transactions on Nuclear Science 58 (6), 3060-3066, 2011 | 32 | 2011 |
| Differential charge cancellation (DCC) layout as an RHBD technique for bulk CMOS differential circuit design RW Blaine, NM Atkinson, JS Kauppila, SE Armstrong, NC Hooten, ... IEEE Transactions on Nuclear Science 59 (6), 2867-2871, 2012 | 30 | 2012 |
| Significance of strike model in circuit-level prediction of charge sharing upsets AM Francis, D Dimitrov, J Kauppila, A Sternberg, M Alles, J Holmes, ... IEEE Transactions on Nuclear Science 56 (6), 3109-3114, 2009 | 30 | 2009 |
| The impact of charge collection volume and parasitic capacitance on SEUs in SOI-and bulk-FINFET D flip-flops DR Ball, ML Alles, JS Kauppila, RC Harrington, JA Maharrey, ... IEEE Transactions on Nuclear Science 65 (1), 326-330, 2017 | 29 | 2017 |
| An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology HB Wang, L Chen, R Liu, YQ Li, JS Kauppila, BL Bhuva, K Lilja, SJ Wen, ... IEEE Transactions on Nuclear Science 63 (6), 3003-3009, 2016 | 28 | 2016 |
Lloyd MassengillVanderbilt UniversityVerified email at vanderbilt.edu
