| A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure CC Liu, SJ Chang, GY Huang, YZ Lin IEEE Journal of Solid-State Circuits 45 (4), 731-740, 2010 | 1462 | 2010 |
| A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation CC Liu, SJ Chang, GY Huang, YZ Lin, CM Huang, CH Huang, L Bu, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 386-387, 2010 | 372 | 2010 |
| A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18 µm CMOS CC Liu, SJ Chang, GY Huang, YZ Lin, CM Huang 2010 Symposium on VLSI Circuits, 241-242, 2010 | 184 | 2010 |
| A 1-µW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications GY Huang, SJ Chang, CC Liu, YZ Lin IEEE Journal of Solid-State Circuits 47 (11), 2783-2795, 2012 | 183 | 2012 |
| A 10 bit 320 MS/s low-cost SAR ADC for IEEE 802.11 ac applications in 20 nm CMOS CC Liu, CH Kuo, YZ Lin IEEE Journal of Solid-State Circuits 50 (11), 2645-2654, 2015 | 165 | 2015 |
| 10-bit 30-MS/s SAR ADC using a switchback switching method GY Huang, SJ Chang, CC Liu, YZ Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (3), 584-588, 2012 | 121 | 2012 |
| A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS YZ Lin, CC Liu, GY Huang, YT Shyu, YT Liu, SJ Chang IEEE Transactions on Circuits and Systems I: Regular Papers 60 (3), 570-581, 2013 | 92 | 2013 |
| Effective and efficient approach for power reduction by using multi-bit flip-flops YT Shyu, JM Lin, CP Huang, CW Lin, YZ Lin, SJ Chang IEEE transactions on very large scale integration (vlsi) systems 21 (4), 624-635, 2012 | 88 | 2012 |
| 20.2 A 40MHz-BW 320MS/s passive noise-shaping SAR ADC with passive signal-residue summation in 14nm FinFET YZ Lin, CY Lin, SC Tsou, CH Tsai, CH Lu 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 330-332, 2019 | 77 | 2019 |
| A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS YZ Lin, CC Liu, GY Huang, YT Shyu, SJ Chang 2010 Symposium on VLSI Circuits, 243-244, 2010 | 73 | 2010 |
| An asynchronous binary-search ADC architecture with a reduced comparator count YZ Lin, SJ Chang, YT Liu, CC Liu, GY Huang IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 1829-1837, 2010 | 71 | 2010 |
| A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme YZ Lin, CW Lin, SJ Chang IEEE Transactions on very large scale integration (VLSI) systems 18 (3), 509-513, 2009 | 70 | 2009 |
| A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS YZ Lin, SJ Chang, YT Liu, CC Liu, GY Huang 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 58 | 2009 |
| A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS YZ Lin, CH Tsai, SC Tsou, CH Lu 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 46 | 2016 |
| A 10b 200MS/s 0.82 mW SAR ADC in 40nm CMOS GY Huang, SJ Chang, YZ Lin, CC Liu, CP Huang 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 289-292, 2013 | 43 | 2013 |
| A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS YZ Lin, CH Tsai, SC Tsou, RX Chu, CH Lu 2017 Symposium on VLSI Circuits, C234-C235, 2017 | 37 | 2017 |
| A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance GY Huang, CC Liu, YZ Lin, SJ Chang 2009 IEEE Asian Solid-State Circuits Conference, 157-160, 2009 | 34 | 2009 |
| A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS YZ Lin, YT Liu, SJ Chang 2007 IEEE Custom Integrated Circuits Conference, 213-216, 2007 | 30 | 2007 |
| 27.5 An 80MHz-BW 640MS/s time-interleaved passive noise-shaping SAR ADC in 22nm FDSOI process CY Lin, YZ Lin, CH Tsai, CH Lu 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 378-380, 2021 | 23 | 2021 |
| Subrange analog-to-digital converter and method thereof SJ Chang, YZ Lin, CC Liu US Patent 8,310,388, 2012 | 23 | 2012 |
