| A new efficient topological structure for floorplanning in 3D VLSI physical design AK Khan, R Vatsa, S Roy, B Das 2014 IEEE International Advance Computing Conference (IACC), 696-701, 2014 | 8 | 2014 |
| Via minimization for multi-layer channel routing in VLSI design B Das, AK Mahato, AK Mahato 2014 Fourth International Conference on Communication Systems and Network …, 2014 | 3 | 2014 |
| Architecture and implementation issues of multi-core processors and caching–a survey B Das, AK Mahato, AK Khan International Conference on Advances in Electronics, 2023 | 2 | 2023 |
| A new algorithm with minimum track for four layer channel routing in VLSI design AK Khan, B Das 2013 International Conference on Computer Communication and Informatics, 1-5, 2013 | 2 | 2013 |
| A Review on Channel Routing On VLSI Physical Design AK Khan, B Das, TK Bayen IOSR Journal of Computer Engineering 5 (1), 41-48, 2012 | 1 | 2012 |
| A novel approach for constrained via minimization problem in VLSI channel routing B Das, A kumar Mahato, AK Khan 2015 International Conference on Electronic Design, Computer Networks …, 2015 | | 2015 |
| A heuristic algorithm for via minimization in VLSI channel routing B Das, AK Mahato, AK Khan 2014 First International Conference on Automation, Control, Energy and …, 2014 | | 2014 |
| AN EFFICIENT APPROACH FOR FOUR-LAYER CHANNEL ROUTING IN VLSI DESIGN AK Khan, B Das, TK Bayen International Journal of VLSI Design & Communication Systems 3 (5), 147, 2012 | | 2012 |
| A REVIEW ON MULTI-LAYER CHANNEL ROUTING IN VLSI DESIGN AK Khan, B Das | | |
