Power-aware placement Y Cheon, PH Ho, AB Kahng, S Reda, Q Wang Proceedings of the 42nd annual Design Automation Conference, 795-800, 2005 | 166 | 2005 |
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip Y Cheon, PH Ho US Patent 7,546,567, 2009 | 38 | 2009 |
Design hierarchy guided multilevel circuit partitioning Y Cheon, DF Wong Proceedings of the 2002 international symposium on Physical design, 30-35, 2002 | 20 | 2002 |
A min-cost flow based detailed router for FPGAs S Lee, Y Cheon, MDF Wong ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 18 | 2003 |
Method and apparatus for reducing power consumption in an integrated circuit chip PH Ho, Y Cheon, Q Wang US Patent 7,257,782, 2007 | 17 | 2007 |
Stable multiway circuit partitioning for eco Y Cheon, S Lee, MDF Wong ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 9 | 2003 |
Method and apparatus for partitioning an integrated circuit chip PH Ho, Y Cheon US Patent 7,260,802, 2007 | 7 | 2007 |
Clock tree synthesis for low power and low susceptibility to variation Y Cheon, PH Ho, W Hou, Y Liu, D Wang 2007 7th International Conference on ASIC, 1333-1333, 2007 | 2 | 2007 |
Crowdedness-balanced multilevel partitioning for uniform resource utilization Y Cheon, MDF Wong Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 2 | 2005 |
Multilevel circuit partitioning for computer-aided VLSI design Y Cheon The University of Texas at Austin, 2004 | 2 | 2004 |
Power-Aware Placement ATG Synopsys, Y Cheon, PH Ho, R Damiano | | |