Enabling a reliable STT-MRAM main memory simulation K Asifuzzaman, RS Verdejo, P Radojković Proceedings of the International Symposium on Memory Systems, 283-292, 2017 | 22 | 2017 |
Rethinking cycle accurate DRAM simulation S Li, RS Verdejo, P Radojković, B Jacob Proceedings of the International Symposium on Memory Systems, 184-191, 2019 | 19 | 2019 |
Main memory latency simulation: the missing link RS Verdejo, K Asifuzzaman, M Radulovic, P Radojković, E Ayguadé, ... Proceedings of the International Symposium on Memory Systems, 107-116, 2018 | 17 | 2018 |
PROFET: Modeling system performance and energy without simulating the CPU M Radulovic, R Sánchez Verdejo, P Carpenter, P Radojković, B Jacob, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 3 (2 …, 2019 | 10 | 2019 |
Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators RS Verdejo, P Radojkovic 2017 International Conference on High-Performance Computing & Simulation …, 2017 | 7 | 2017 |
Performance and power estimation of STT-MRAM main memory with reliable system-level simulation K Asifuzzaman, RS Verdejo, P Radojković ACM Transactions on Embedded Computing Systems (TECS) 21 (1), 1-25, 2022 | 5 | 2022 |
HPC memory systems: Implications of system simulation and checkpointing R Sánchez Verdejo Universitat Politècnica de Catalunya, 2022 | | 2022 |
Detailed tuning and validation of hardware simulators through microbenchmarks R Sánchez Verdejo, P Radojković Book of abstracts, 57-58, 2018 | | 2018 |